PURPOSE:To enable the device structure wherein the side-gate effect does not occur, by forming a second conductivity type diffusion layer which does not come into contact with the channel part of a first conductivity type field effect transistor, but comes into contact with the source diffusion layer. CONSTITUTION:The title field effect transistor FET is constituted of the following; a semi-insulating substrate 1, a drain N-type diffusion layer 2, a gate electrode 3, a channel 4, a source N-type diffusion layer 5, a P-type absorption layer 6 to absorb hole being a second conductivity type carrier, a drain electrode 7 and a source electrode 8. The N-type layers 2, 4, 5 are formed by ion implantation of silicon, and turn to high concentration layers. The P-type layer 6 is formed by ion implantation of Zn, Mg, Be, etc. Source drain ion implantation can serve as annealing. As the result, a P-N junction being in contact with the P-type layer 6 and the N-type layer 2 or the N-type layer 5 turns to a high concentration region, and the leak current becomes large, so that floating hole is sufficiently absorbed without connection applying metal electrodes. When the P-type layer is provided with an ohmic electrode of metal, low concentration is available to the P-type layer.